----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:26:11 12/03/2014 
-- Design Name: 
-- Module Name:    ex_mem - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ex_mem is
	port(
		clk:in std_logic;
		wb_in,wm_in,rm_in:in std_logic;
		rd_in:in std_logic_vector(3 downto 0);
		result_in,data2_in:in std_logic_vector(15 downto 0);
		wb_out,wm_out,rm_out:out std_logic;
		rd_out:out std_logic_vector(3 downto 0);
		result_out,data2_out:out std_logic_vector(15 downto 0)
	);
end ex_mem;

architecture Behavioral of ex_mem is
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			wb_out<=wb_in;
			wm_out<=wm_in;
			rm_out<=rm_in;
			rd_out(3 downto 0)<=rd_in(3 downto 0);
			result_out(15 downto 0)<=result_in(15 downto 0);
			data2_out(15 downto 0)<=data2_in(15 downto 0);
		end if;
	end process;



end Behavioral;

